This invention relates generally to large scale data processing systems and more particularly to systems employing a plurality of processors operating more or less simultaneously in order to reduce overall program execution time.
In the development of digital computers a most important design goal has always been to maximize their operating speed, i.e., the amount of data that can be processed in a unit of time. It has become increasingly apparent in recent times that two important limiting conditions exist within the present framework of computer design. These are the limits of component speed and of serial machine organization. To overstep these limitations two different types of parallel operating systems have been developed.
First, multiprocessing systems have been developed wherein a number of quite independent processors have been linked together to operate in parallel on differing portions of a program or job in order to speed execution of that program or job. Frequently, the processors are linked together in a network loop or similar fashion, thus greatly slowing the cooperation between processors. When the processors are linked together by a parallel and much faster network such as a crossbar network, the network control mechanism and the cost and reliability of the network quickly become unwieldly for a reasonable large number of processors.
Second, high speed parallel locked-step processing systems have been developed providing an array of processing elements under the control of a single control unit.
As speed requirements of computation have continued to increase, systems employing greater numbers of parallel memory modules have been developed. One such system has in the order of 64 parallel memories, see U.S. Pat. No. 3,537,074, issued Oct. 27, 1970, to R. A. Stokes et al, and assigned to the assignee of the present invention. However, parallel processors have not been without their own problems.
Primarily, parallel processors are often so far removed from the conventional scaler processors that they are hard to program. Secondarily, parallel processors are fashioned to operate efficiently with vectorized data but are quite inefficient operating upon scaler data. Finally, parallel processors, being found operating a locked-step fashion in prior art force all processors in the parallel array thereof to perform in synchronization whether or not such operation is needed in all processors.
The manner of difficulty in programming the parallel array has been greatly eased by the incorporation and use of the computational envelope approach as disclosed in U.S. Pat. No. 4,101,960, issued July 18, 1978, in the name of Stokes et al, and assigned to the assignee of the present invention. Briefly in the computational envelope approach a host or support processor of a general processing variety (such as a Burroughs B7800) functions as an I/O controller and user interface. Special purpose jobs are transferred in their entirety (program and data) to a large high speed secondary storage system or data base memory and from hence to the array memory modules and array processor for processing. During the special purpose processing period the front end support or host processor is freed for other processing jobs. Once the complete special purpose job or task is executed by the array processors, the resultants therefrom are returned through the array memories and the data base memory to the support processor for output to the user.
It is an object of the present invention to provide a processing array functioning in the computational envelope mode of operation.
It is another object of the present invention to provide an array of processors which can function efficienty and effectively both in multiprocessing and parallel processing.
It is yet another object of the present invention to provide a method and apparatus for quickly and efficiently synchronizing an array of independent processors to begin a task in parallel.